2次シグマデルタADC用のSinc3フィルターのVerilog実装

Verilog Implementation Sinc3 Filter

Sinc3フィルターは2次インクリメンタルシグマデルタADCで一般的に使用され、その伝達関数は次のとおりです。

この記事では、約22ビットのインクリメンタルシグマデルタADCで使用されるL = 3およびM = 1600のSINC3フィルターを実装します。
ここにいくつかVerilog code to implement sinc3 filter。があります。

// An highlighted block module sinc3 (in,clk,clk_clc,en,resu) input in,clk,clk_clc,en output resu reg [1600:1] bs //Save input reg [10:0] bs2 [1600:1] //memory saves the value of the first level output reg [21:0] bs3 [1600:1] //memory saves the value of the second level output reg [10:0] count,count_1//Used to specify the address of the memory reg [10:0] temp2//Temporarily store the data before 1600 clocks of the first level reg [21:0] temp3//Temporarily store the data before 1600 clocks of the second level reg [32:0] resu reg [10:0] count_clc//Used to clear the address count when memory root@xxxxx(posedge clk_clc)//Perform memory clear begin if(en==1) count_clc<=11'b0 else if (count_clc<11'd1600) count_clc<=count_clc+1'b1 else count_clc<=1'b1 end root@xxxxx(posedge clk_clc) begin if(en==0) begin bs[count_clc]<=0 bs2[count_clc]<=0 bs3[count_clc]<=0 end end //End of register clearing root@xxxxx(posedge clk) begin if(en==0) begin count<=11'd1 count_1<=11'd1600 end else if (count==11'd1600) begin count<=11'd1 count_1<=count end else begin count<=count+1'b1 count_1<=count end end root@xxxxx(posedge clk) begin if (en==1) begin bs[count]<=in end end root@xxxxx(posedge clk) begin if(en==0) temp2<=0 else begin temp2<=bs2[count] bs2[count]<=bs2[count_1]+in-bs[count] end end root@xxxxx(posedge clk) begin if(en==0) temp3<=0 else begin temp3<=bs3[count] bs3[count]<=bs3[count_1]+bs2[count_1]-temp2 end end root@xxxxx(posedge clk) begin if(en==0) resu<=0 else begin resu<=resu+bs3[count_1]-temp3 end end endmodule